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NS486SXF 数据表(PDF) 39 Page - National Semiconductor (TI) |
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NS486SXF 数据表(HTML) 39 Page - National Semiconductor (TI) |
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39 / 44 page ![]() 30 Device Specifications (Continued) Symbol Parameter Min Max Units tSINT Delay from Stop Bit to Set Interrupt 2 BAUDOUT Cycles tSTI Delay from Start Bit to IRQ 8 BAUDOUT Cycles tSI Delay from Initial Write to IRQ 16 24 BAUDOUT Cycles tIRS Delay from IRQ Reset to Tx Start 8 24 BAUDOUT Cycles tMDO Delay from Write to Output 40 ns tRIM Delay to Reset IRQA from Read 78 ns tSIM Delay to Set IRQ from Modem Input 40 ns BAUDOUT Cycle e Input Clock Frequency 16 x Baudrate Divisor Input Clock Frequency e OSCX1 Frequency UART Clock Divisor Registers Divisor Latch Holds Baudrate Divisor EF70 holds UART Clock Divisor TLEE12514 – 28 TLEE12514 – 29 FIGURE 3-18 UART IRQ Timing http www nationalcom 39 |
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