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NSAM266SAA/V 数据表(PDF) 16 Page - National Semiconductor (TI) |
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NSAM266SAA/V 数据表(HTML) 16 Page - National Semiconductor (TI) |
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16 / 52 page ![]() 10 Hardware (Continued) INPUT SIGNALS Symbol Figure Description Reference Conditions Min (ns) tCDIh 1-15 CDIN Hold After RE CTTL 00 tCDIs 1-15 CDIN Setup Before RE CTTL 110 tDIh 1-17 Data in Hold (D07) After RE CTTL T1 T3 or TI 00 tDIs 1-17 Data in Setup (D07) Before RE CTTL T1 T3 or TI 150 tMMDINh 1-20 Master MICROWIRE Data In Hold After RE CTTL 00 tMMDINs 1-20 Master MICROWIRE Data In Setup Before RE CTTL 110 tMWCKh 1-18 MICROWIRE Clock High (Slave) At 20V (Both Edges) 1000 tMWCKI 1-18 MICROWIRE Clock Low (Slave) At 08V (Both Edges) 1000 tMWCKp 1-18 MICROWIRE Clock Period (Slave) (Note A) RE MWCLK to next RE MWCLK 25 ms tMWCLKh 1-18 MWCLK Hold After MWCS becomes Inactive 500 tMWCLKs 1-18 MWCLK Setup Before MWCS becomes Active 1000 tMWCSh 1-18 MWCS Hold After FE MWCLK 500 tMWCSs 1-18 MWCS Setup Before RE MWCLK 1000 tMWDIh 1-18 MWDIN Hold After RE MWCLK 500 tMWDIs 1-18 MWDIN Setup Before RE MWCLK 1000 tPWR 1-24 Power Stable to RESET RE (Note B) After VCC reaches 45V 300 ms tRSTw 1-23 RESET Pulse Width At 08V (Both Edges) 100 ms tXh 1-22 CLKIN High At 20V (Both Edges) tX1p 2 b 5 tXI 1-22 CLKIN Low At 08V (Both Edges) tX1p 2 b 5 tXp 1-22 CLKIN Clock Period RE CLKIN to next RE CLKIN 244 Note A Guaranteed by design but not fully tested in power-down mode Note B Guaranteed by design but not fully tested http www nationalcom 16 |
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