STM32L476RG datasheet(54/232 Pages) STMICROELECTRONICS

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Functional overview

STM32L476xx

54/232

DocID025976 Rev 4

3.36

Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external flash is memory mapped and is seen by the

system as if it were an internal memory

The Quad SPI interface supports:

•

Three functional modes: indirect, status-polling, and memory-mapped

•

SDR and DDR support

•

Fully programmable opcode for both indirect and memory mapped mode

•

Fully programmable frame format for both indirect and memory mapped mode

•

Each of the 5 following phases can be configured independently (enable, length,

single/dual/quad communication)

–

Instruction phase

–

Address phase

–

Alternate bytes phase

–

Dummy cycles phase

–

Data phase

•

Integrated FIFO for reception and transmission

•

8, 16, and 32-bit data accesses are allowed

•

DMA channel for indirect mode operations

•

Programmable masking for external flash flag management

•

Timeout management

•

Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

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