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NSC800D 数据表(PDF) 48 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 NSC800D
功能描述  NSC800TM High-Performance Low-Power CMOS Microprocessor
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

NSC800D 数据表(HTML) 48 Page - National Semiconductor (TI)

Back Button NSC800D Datasheet HTML 44Page - National Semiconductor (TI) NSC800D Datasheet HTML 45Page - National Semiconductor (TI) NSC800D Datasheet HTML 46Page - National Semiconductor (TI) NSC800D Datasheet HTML 47Page - National Semiconductor (TI) NSC800D Datasheet HTML 48Page - National Semiconductor (TI) NSC800D Datasheet HTML 49Page - National Semiconductor (TI) NSC800D Datasheet HTML 50Page - National Semiconductor (TI) NSC800D Datasheet HTML 51Page - National Semiconductor (TI) NSC800D Datasheet HTML 52Page - National Semiconductor (TI) Next Button
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129 Rotate and Shift (Continued)
RR
m1
Rotate the data in memory location m1 right through the
carry
TLC5171 – 67
S Set if result is negative
Z Set if result is zero
H Reset
PV Set if result parity is even
N Reset
C Set according to bit 0 of m1
76543210
1
1
0
0
1
0
1
1
RR (HL)
00011110
Timing
M cycles
4
T states
15 (4 4 4 3)
Addressing Mode
Register Indirect
76
5
4
3210
RR (IX a d) (for NX e 0)
11NX 11101
RR (IY a d) (for NX e 1)
11
0
0
1011
d
00
0
1
1110
Timing
M cycles
6
T states
23 (4 4 3 5 4 3)
Addressing Mode
Indexed
SLA
m1
Shift the data in memory location m1 left arithmetic
TLC5171 – 68
S Set if result is negative
Z Set if result is zero
H Reset
PV Set if result parity is even
N Reset
C Set according to bit 7 of m1
76543210
1
1
0
0
1
0
1
1
SLA (HL)
00100110
Timing
M cycles
4
T states
15 (4 4 4 3)
Addressing Mode
Register Indirect
76
5
4
3210
SLA (IX a d) (for NX e 0)
11NX 11101
SLA (IY a d) (for NX e 1)
11
0
0
1011
d
00
1
0
0110
Timing
M cycles
6
T states
23 (4 4 3 5 4 3)
Addressing Mode
Indexed
SRA
m1
Shift the data in memory location m1 right arithmetic
TLC5171 – 69
S Set if result is negative
Z Set if result is zero
H Reset
PV Set if result parity is even
N Reset
C Set according to bit 0 of m1
76543210
1
1
0
0
1
0
1
1
SRA (HL)
00101110
Timing
M cycles
4
T states
15 (4 4 4 3)
Addressing Mode
Register Indirect
76
5
4
3210
SRA (IX a d) (for NX e 0)
11NX 11101
SRA (IY a d) (for NX e 1)
11
0
0
1011
d
00
1
0
1110
Timing
M cycles
6
T states
23 (4 4 3 5 4 3)
Addressing Mode
Indexed
SRL
m1
Shift right logical the data in memory location m1
TLC5171 – 70
S Reset
Z Set if result is zero
H Reset
PV Set if result parity is even
N Reset
C Set according to bit 0 of m1
48



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