OMAP3530ECUS datasheet(164/265 Pages) TI1

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gpmc_clk

gpmc_ncsx

gpmc_a[26:17]

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

Address(MSB)

Address(LSB)

OUT

F15

F17

F14

030-025

OMAP3530, OMAP3525

SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013

www.ti.com

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-6. GPMC/Multiplexed NOR Flash – Synchronous Burst Write

6.4.1.2

GPMC/NOR Flash Interface Asynchronous Timing

Table 6-7 and Table 6-8 assume testing over the recommended operating conditions (see Figure 6-7

through Figure 6-12) and electrical characteristic conditions.

Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

1.8

Input signal fall time

1.8

Output Conditions

CLOAD

Output load capacitance

15.94

Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1) (2)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FI1

Maximum output data generation delay from internal

6.5

9.1

13.7

functional clock

FI2

Maximum input data capture delay by internal

5.6

8.1

functional clock

FI3

Maximum device select generation delay from internal

6.5

9.1

13.7

functional clock

FI4

Maximum address generation delay from internal

6.5

9.1

13.7

functional clock

(1)

The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.

(2)

Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

164

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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