30

Symbol

Parameter

Conditions

Min

Max

Units

Transmitter

Delay from WR WR (WR THR)

100 pF Load

175

ns

to Reset Interrupt

Delay from RD RD (RD IIR) to Reset

100 pF Load

250

ns

Interrupt (THRE)

Delay from Initial INTR Reset to Transmit

824

BAUDOUT

Start

Cycles

Delay from Initial Write to Interrupt

(Note 1)

16

24

BAUDOUT

Cycles

Delay from Stop to Interrupt (THRE)

(Note 1)

88

BAUDOUT

Cycles

Delay from Start to TXRDY active

100 pF Load

8

BAUDOUT

Cycles

Delay from Write to TXRDY inactive

100 pF Load

195

ns

Modem Control

Delay from WR WR (WR MCR) to

100 pF Load

200

ns

Output

Delay from RD RD to Reset Interrupt

100 pF Load

250

ns

(RD MSR)

Delay from MODEM Input to Set Interrupt

100 pF Load

250

ns

Note 1

This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode

Operation)

Note 2

These specifications are preliminary

40

External Clock Input (240 MHz Max)

TLC8652 – 2

AC Test Points

TLC8652 – 3

Note 1

The 24V and 04V levels are the voltages that the inputs are driven to during AC testing

Note 2

The 20V and 08V levels are the voltages at which the timing tests are made

BAUDOUT Timing

TLC8652 – 4

5