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PC16550DN 数据表(PDF) 13 Page - National Semiconductor (TI) |
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PC16550DN 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 22 page  70 Connection Diagrams (Continued) TQFP Package TLC8652 – 26 Order Number PC16550DVEF See NS Package Number VEF44A Chip Carrier Package TLC8652 – 18 Top View Order Number PC16550DV See NS Package Number V44A TABLE I UART Reset Configuration RegisterSignal Reset Control Reset State Interrupt Enable Register Master Reset 0000 0000 (Note 1) Interrupt Identification Register Master Reset 0000 0001 FIFO Control Master Reset 0000 0000 Line Control Register Master Reset 0000 0000 MODEM Control Register Master Reset 0000 0000 Line Status Register Master Reset 0110 0000 MODEM Status Register Master Reset XXXX 0000 (Note 2) SOUT Master Reset High INTR (RCVR Errs) Read LSRMR Low INTR (RCVR Data Ready) Read RBRMR Low INTR (THRE) Read IIRWrite THRMR Low INTR (Modem Status Changes) Read MSRMR Low OUT 2 Master Reset High RTS Master Reset High DTR Master Reset High OUT 1 Master Reset High RCVR FIFO MRFCR1 FCR0 DFCR0 All Bits Low XMIT FIFO MRFCR1 FCR0 DFCR0 All Bits Low Note 1 Boldface bits are permanently low Note 2 Bits 7–4 are driven by the input signals 13 |
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