Symbol

Parameter

Conditions

Min

Max

Units

TRANSMITTER

Delay from WR (WR THR)

40

ns

to Reset Interrupt

Delay from RD (RD IIR) to Reset

40

ns

Interrupt (THRE)

Delay from Initial INTR Reset

824

BAUDOUT

to Transmit Start

Cycles

Delay from Initial Write to Interrupt

(Note 1)

16

24

BAUDOUT

Cycles

Delay from Start to Interrupt (THRE)

(Note 1)

8

BAUDOUT

Cycles

Delay from Start to TXRDY Active

8

BAUDOUT

Cycles

Delay from Write to TXRDY Inactive

25

ns

MODEM CONTROL

Delay from WR (WR MCR)

40

ns

to Output

Delay to Reset Interrupt from

78

ns

RD (RD MSR)

Delay to Set Interrupt from MODEM Input

40

ns

Note 1

This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode

Operation)

External Clock Input (24 MHz Max)

TLC9426 – 2

AC Test Points

TLC9426 – 3

Note 2

The 24V and 04V levels are the voltages that the inputs are driven to during AC testing

Note 3

The 20V and 08V levels are the voltages at which the timing tests are made

BAUDOUT Timing

TLC9426 – 4

5