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PC16552D 数据表(PDF) 13 Page - National Semiconductor (TI) |
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PC16552D 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 21 page ![]() 80 Registers TABLE I Register Addresses DLAB1 CHSL A2 A1 A0 Register 0 1 0 0 0 Receiver Buffer (Read) Transmitter Holding Register (Write) 0 1 0 0 1 Interrupt Enable C 0 1 0 1 0 Interrupt Identification (Read) H 0 1 0 1 0 FIFO Control (Write) A X 1 0 1 1 Line Control N X 1 1 0 0 MODEM Control N X 1 1 0 1 Line Status E X 1 1 1 0 MODEM Status L X 1 1 1 1 Scratch 1 1 0 0 0 Divisor Latch 1 (Least Significant Byte) 1 1 0 0 1 Divisor Latch (Most Significant Byte) 1 1 0 1 0 Alternate Function DLAB2 CHSL A2 A1 A0 Register 0 0 0 0 0 Receiver Buffer (Read) Transmitter Holding Register (Write) 0 0 0 0 1 Interrupt Enable C 0 0 0 1 0 Interrupt Identification (Read) H 0 0 0 1 0 FIFO Control (Write) A X 0 0 1 1 Line Control N X 0 1 0 0 MODEM Control N X 0 1 0 1 Line Status E X 0 1 1 0 MODEM Status L X 0 1 1 1 Scratch 1 0 0 0 0 Divisor Latch 2 (Least Significant Byte) 1 0 0 0 1 Divisor Latch (Most Significant Byte) 1 0 0 1 0 Alternate Function 13 |
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