PC87200 datasheet(13/33 Pages) NSC

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5.0 Pin Descriptions (Continued)

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5.3.5 Miscellaneous Signals (Continued)

IOCS16#

I/O Chip Select 16

IOCS16# is asserted by 16-bit ISA I/O devices based on an asynchronous de-

code of SA[15:0] to indicate that SD[15:0] may be used to transfer data (8-bit ISA

I/O devices use SD[7:0]).

IOR#

I/O

I/O Read

IOR# is asserted to request an ISA I/O slave to drive data onto the data bus.

IOW#

I/O

I/O Write

IOW# is asserted to request an ISA I/O slave to accept data from the data bus.

MEMCS16#

I/O

Memory Chip Select 16

MEMCS# is asserted by 16-bit ISA memory devices based on an asynchronous

decode of SA[23:17] to indicate that SD[15:0] may be used to transfer data (8-

bit ISA memory devices use SD[7:0]).

MEMR#

I/O

Memory Read

MEMR# is asserted for all memory read accesses (including those above 1MB).

It enables 16-bit memory slaves to decode the memory address on SA[23:0].

MEMW#

I/O

Memory Write

MEMW# is asserted for all memory write accesses (including those above 1MB).

It enables 16-bit memory slaves to decode the memory address on SA[23:0].

AEN

Address Enable

AEN asserted indicates to ISA memory devices that a valid address for a DMA

transfer is present on SA[23:0], and for I/O devices to ignore this address and

any data on the ISA bus.

IRQ[15:14], [12:9],

[7:3]

37,38,

36,35,

34,5,

132,131,

130,129,

128

ISA Bus Interrupt Request

IRQ inputs are interrupts that indicate ISA devices or other devices requesting a

CPU interrupt service.

DREQ[7:5],

DREQ[3:0]

58 52,

46,134,

7,137,42

DMA Request - Channels [7:5], [3:0]

DREQ inputs are asserted by ISA DMA devices to request a DMA transfer. The

request must remain asserted until the corresponding DACK# is asserted.

DACK[7:5]#,

DACK[3:0]#

57,51,

45,133,

6,136,41

DMA Acknowledge- Channels [7:5], [3:0]

DACK# outputs are asserted to indicate when a DREQ is granted and the start

of a DMA cycle.

Terminal Count

TC signals the final data transfer of a DMA transfer.

IOCHK#

I/O channel check

Asserted by an ISA device indicating an error condition.

Signal Name

Pin No.

Type

Description

Signal Name

Pin No.

Type

Description

SERIRQ

127

I/O

s/t/s

Serial IRQ

This is a one pin bus that conveys interrupt source information to the chipset.

PROHIBIT

138

PROHIBIT

An active high signal from the chipset indicating that the PC87200 should not act

as the subtractive decode agent on the PCI bus.

BPD#

BIOS Positive Decode (active low)

When this pin is asserted low after BALE is detected high after reset, the PRO-

HIBIT signal will be a don’t care. The BIOS memory range will be positively de-

coded and claimed as such. All other cycles are still subtractively decoded.

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