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7.2 Chipset Register Space

The Chipset Register Space of the PC87200 is comprised

of one function with PCI header registers. There is no

memory or I/O mapped register.

7.2.1 Bridge Configuration Registers - Function 0

The register space designated as Function 0 (F0) contains

registers used to configure features and functionality

unique to the PC87200. All registers in Function 0 are

directly accessed (i.e., there are no memory or I/O mapped

registers in F0). Table 4 gives the bit formats for these reg-

isters.

IMPORTANT: Register bits marked internal use should

not be overwritten, else error will occur.

Table 4. Bridge Configuration Registers

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 100Bh

Index 02h-03h

Device Identification Register (RO)

Reset Value =0021h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0107h

15:10

Reserved — Set to 0.

9

Fast Back-to-Back Enable (Read Only) — This function is not supported when PC87200 is a master. It is al-

ways disabled (must always be set to 0).

8

SERR# — Allow SERR# assertion on detection of special errors: 0 = Disable; 1 = Enable.

7

Wait Cycle Control (Read Only) — This function is not supported in PC87200. It is always disabled (bit is set

to 0).

6

Parity Error — Allow PC87200 to check for parity errors on PCI cycles for which it is a target, and to assert

PERR# when a parity error is detected: 0 = Disable; 1 = Enable.

5

VGA Palette Snoop Enable (Read Only) — This function is not supported in PC87200. It is always disabled

(bit is set to 0).

4

Memory Write and Invalidate —

Allow PC87200 to do memory write and invalidate cycles, if the PCI

cache line register is set to 16 bytes (04h). 0=Disable, 1=Enable.

3

Special Cycles — This function is not supported. It must always be set to 0.

2

Bus Master — Allow PC87200 bus mastering capabilities: 0 = Disable; 1 = Enable. Set this bit to 1.

1

Memory Space — Allow PC87200 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable.

PC87200 will only respond to memory cycles destined for the ISA bus as none of its internal functions are

memory-mapped.

0

I/O Space — Allow PC87200 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable.

Index 06h-07h

PCI Status Register (R/W)

Reset Value = 0280h

15

Detected Parity Error — This bit is set whenever a parity error is detected. Write 1 to clear.

14

Signaled System Error — This bit is set whenever PC87200 asserts SERR# active. Write 1 to clear.

13

Received Master Abort — This bit is set whenever a master abort cycle occurs. A master abort will occur

when a PCI cycle is not claimed, except for special cycles. Write 1 to clear. Register is cleared after RMA is

read.

12

Received Target Abort — This bit is set whenever a target abort is received while the PC87200 is the master

for the PCI cycle. Write 1 to clear.

11

Signaled Target Abort — This bit is set whenever the PC87200 signals a target abort. This occurs when an

address parity error occurs for an address that hits in the active address decode space of the PC87200. Write

1 to clear.

10:9

DEVSEL# Timing — These bits are always 01, as the PC87200 will always respond to cycles for which it is

an active target with medium DEVSEL# timing.

00 = Fast

01 = Medium

10 = Slow

11 = Reserved