SC2200 datasheet(39/433 Pages) NSC

39 / 433 page

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Signal Definitions (Continued)

C16

AVSSPLL2

GND

---

C176,2

SLCT

INT

VIO

PMR[23]3 = 0 and

(PMR[27] = 0 and

FPCI_MON = 0)

TFTD15

O1/4

PMR[23]3 = 1 and

(PMR[27] = 0 and

FPCI_MON = 0)

F_C/BE3#

O1/4

PMR[23]3 = 0 and

(PMR[27] = 1 or

FPCI_MON = 1)

C18

PD4

I/O

INT,

O14/14

VIO

PMR[23]3 = 0 and

(PMR[27] = 0 and

FPCI_MON = 0)

TFTD10

O1/4

PMR[23]3 = 1 and

(PMR[27] = 0 and

FPCI_MON = 0)

F_AD4

O14/14

PMR[23]3 = 0 and

(PMR[27] = 1 or

FPCI_MON = 1)

C196,2

PD5

I/O

INT,

O14/14

VIO

PMR[23]3 = 0 and

(PMR[27] = 0 and

FPCI_MON = 0)

TFTD11

O1/4

PMR[23]3 = 1 and

(PMR[27] = 0 and

FPCI_MON = 0)

F_AD5

O14/14

PMR[23]3 = 0 and

(PMR[27] = 1 or

FPCI_MON = 1)

C206,2

PD3

I/O

INT,

O14/14

VIO

PMR[23]3 = 0 and

(PMR[27] = 0 and

FPCI_MON = 0)

TFTD9

O1/4

PMR[23]3 = 1 and

(PMR[27] = 0 and

FPCI_MON = 0)

F_AD3

O14/14

PMR[23]3 = 0 and

(PMR[27] = 1 or

FPCI_MON = 1)

C216,2

PD0

I/O

INT,

O14/14

VIO

PMR[23]3 = 0 and

(PMR[27] = 0 and

FPCI_MON = 0)

TFTD6

O1/4

PMR[23]3 = 1 and

(PMR[27] = 0 and

FPCI_MON = 0)

F_AD0

O14/14

PMR[23]3 = 0 and

(PMR[27] = 1 or

FPCI_MON = 1)

C22

VIO

PWR

---

C23

---

C24

---

C25

VIO

PWR

---

C26

INTB#

(PU22.5)

INPCI

VIO

---

C27

AVSSUSB

GND

---

C28

GPIO9

I/O

(PU22.5)

INTS,

O1/4

VIO

PMR[18] = 0 and

PMR[8] = 0

DCD2#

(PU22.5)

INTS

PMR[18] = 1 and

PMR[8] = 0

IDE_IOW1#

(PU22.5)

O1/4

PMR[18] = 0 and

PMR[8] = 1

SDTEST2

(PU22.5)

O2/5

PMR[18] = 1 and

PMR[8] = 1

Ball

No.

Signal Name

I/O

(PU/PD)

Buffer1

Type

Power

Rail

Configuration

C29

VIO

PWR

---

C30

GPIO7

I/O

(PU22.5)

INTS,

O1/4

VIO

PMR[17] = 0 and

PMR[8] = 0

RTS2#

(PU22.5)

O1/4

PMR[17] = 1 and

PMR[8] = 0

IDE_DACK1#

(PU22.5)

O1/4

PMR[17] = 0 and

PMR[8] = 1

SDTEST0

(PU22.5)

O2/5

PMR[17] = 1 and

PMR[8] = 1

C31

GPIO8

I/O

(PU22.5)

INTS,

O8/8

VIO

PMR[17] = 0 and

PMR[8] = 0

CTS2#

(PU22.5)

INTS

PMR[17] = 1 and

PMR[8] = 0

IDE_DREQ1

(PU22.5)

INTS1

PMR[17] = 0 and

PMR[8] = 1

SDTEST4

(PU22.5)

O2/5

PMR[17] = 1 and

PMR[8] = 1

AD21

I/O

INPCI,

OPCI

VIO

Cycle Multiplexed

A21

OPCI

AD22

I/O

INPCI,

OPCI

VIO

Cycle Multiplexed

A22

OPCI

AD20

I/O

INPCI,

OPCI

VIO

Cycle Multiplexed

A20

OPCI

AD27

I/O

INPCI,

OPCI

VIO

Cycle Multiplexed

I/O

INPCI,

OPCI

AD31

I/O

INPCI,

OPCI

VIO

Cycle Multiplexed

I/O

INPCI,

OPCI

PCICLK1

OPCI

VIO

---

LPC_ROM

(PD100)

INSTRP

Strap(SeeTable 2-

6onpage51.)

VSS

GND

---

FRAME#

I/O

(PU22.5)

INPCI,

OPCI

VIO

---

IOR#

O3/5

VIO

PMR[21] = 0 and

PMR[2] = 0

DOCR#

O3/5

PMR[21] = 0 and

PMR[2] = 1

GPIO14

I/O

(PU22.5)

INTS,

O3/5

PMR[21] = 1 and

PMR[2] = 1

D10

GPIO1

I/O

(PU22.5)

INT,

O3/5

VIO

PMR[23]3 = 0 and

PMR[13] = 0

IOCS1#

(PU22.5)

O3/5

VIO

PMR[23]3 = 0 and

PMR[13] = 1

TFTD12

(PU22.5)

O1/4

VIO

PMR[23]3 =1

D11

TRDE#

O3/5

VIO

PMR[12] = 0

GPIO0

I/O

(PU22.5)

INTS,

O3/5

VIO

PMR[12] = 1

D12

VCCCRT

PWR

---

Ball

No.

Signal Name

I/O

(PU/PD)

Buffer1

Type

Power

Rail

Configuration

Table 2-4.

481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)

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