SC2200 datasheet(97/433 Pages) NSC

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General Configuration Block (Continued)

FM1SD (Shut Down PLL4).

0: PLL4 is enabled.

1: PLL4 is shutdown, unless internal Fast-PCI clock is strapped to 48 MHz.

C48MD (Disable SuperI/O and USB Clock).

0: USB and SuperI/O clock is enabled.

1: USB and SuperI/O clock is disabled.

Reserved. Write as read.

Offset 13h-17h

Reserved - RSVD

Offset 18h-1Bh

PLL3 Configuration Register - PLL3C (R/W)

Reset Value: E1040005h

31:24

MFFC (MFF Counter Value).

Fvco

= OSCCLK * MFBC / (MFFC * MOC)

OSCCLK = 27 MHz

23:19

Reserved. Write as read.

18:11

MFBC (MFB Counter Value).

Fvco

= OSCCLK * MFBC / (MFFC * MOC)

OSCCLK = 27 MHz

10:7

Reserved. Write as read

Reserved. Must be set to 0.

5:0

MOC (MO Counter Value).

Fvco

= OSCCLK * MFBC / (MFFC * MOC)

OSCCLK = 27 MHz

Offset 1Eh-1Fh

Core Clock Frequency Control Register - CCFC (R/W)

Reset Value: Strapped Value

This register controls the configuration of the core clock multiplier and the reference clocks.

15:14

Reserved.

Reserved. Must be set to 0.

11:10

Reserved.

9:8

FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module

that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0].

00: 33.3 MHz

01: 48 MHz

10: 66.7 MHz

11: 33.3 MHz

7:4

Reserved.

3:0

MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock

Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is differ-

ent from the multiplier indicated in the MCCM register.

0100:

Multiply by 4

0101:

Multiply by 5

0110:

Multiply by 6

0111:

Multiply by 7

1000:

Multiply by 8

1001:

Multiply by 9

1010:

Multiply by 10

Other: Reserved

Table 3-8. Clock Generator Configuration (Continued)

Bit

Description

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