DocID025059 Rev 3

13/20

STGIPS10C60

Smart shutdown function

20

Figure 6. Smart shutdown timing waveforms

Note:

Refer to Table 11 for internal propagation delay time details.

SD/OD

FROM/TO

CONTROLLER

SMART

SD

LOGIC

SHUT DOWN CIRCUIT

An approximation of the disable time is given by:

where:

HIN/LIN

HVG/LVG

open drain gate

(internal)

comp Vref

CP+

PROTECTION

the driver outputs are set in SD state immediately after the comparator

triggering even if the SD signal has not yet reach the lower input threshold

disable time

SD/OD

AM12947v1