PC97307 datasheet(17/218 Pages) NSC

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Signal/Pin Connection and Description

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DIR

FDC

Output

Group 16

Direction (FDC) – This output signal determines the direction of the

Floppy Disk Drive (FDD) head movement (active = step in, inactive =

step out) during a seek operation. During reads or writes, DIR is

inactive.

DR1,0

88, 87

FDC

Output

Group 16

Drive Select 0 and 1 (FDC) – These active low output signals are

the decoded drive select output signals. DR0 and DR1 are controlled

by Digital Output Register (DOR) bits 0 and 1. They are encoded with

information to control four FDDs when bit 7 of the SuperI/O FDC

Conﬁguration register is 1, as described in Section 2.6.1 on page 36.

See MTR0,1 for more information.

DRATE0

FDC

Output

Group 20

Data Rate 0 (FDC) – This output signal reflects the value of bit 0 of

the Conﬁguration Control Register (CCR) or the Data Rate Select

totem-pole buffered (6 mA sink, 6 mA source).

DRQ3-0

55-52

ISA-Bus

Output

Group 18

DMA Request 0, 1, 2 and 3 – These active high output signals

inform the DMA controller that a data transfer is needed. These DMA

signals can be mapped to the following logical devices: Floppy Disk

Controller (FDC), UART1, UART2 or parallel port.

DSKCHG

FDC

Input

Group 1

Disk Change (FDC) – This input signal indicates whether or not the

drive door has been opened. The state of this pin is available from

the Digital Input Register (DIR). This pin can also be conﬁgured as

the RGATE data separator diagnostic input signal via the MODE

command. See the MODE command in Section 5.7.7 starting on

page 92.

DSR2,1

143, 133

UART1,

UART2

Input

Group 1

Data Set Ready – When low, this signal indicates that the data

transfer device, e.g., modem, is ready to establish a communications

link.

The DSR signal is a modem status input signal whose condition the

CPU can test by reading bit 5 (DSR) of the Modem Status Register

(MSR) for the appropriate channel. Bit 5 is the complement of the

DSR signal. Bit 1 (DDSR) of the MSR indicates whether the DSR

input signal has changed state since the previous reading of the

MSR.

Whenever the DDSR bit of the MSR is set, an interrupt is generated

if modem status interrupts are enabled.

DSTRB

119

Parallel Port

Output

Group 23

Data Strobe (EPP) – This signal is used in EPP mode as a data

strobe. It is active low.

DSTRB is multiplexed with AFD. See Table 6-12 on page 134 for

more information.

DTR2,1

144, 134

UART1,

UART2

Output

Group 17

Data Terminal Ready – When low, this output signal indicates to the

modem or other data transfer device that the UART1 or UART2 is

ready to establish a communications link.

The DTR signal can be set active low by programming bit 0 (DTR) of

the Modem Control Register (MCR) to high (1).

A Master Reset (MR) deactivates this signal high, and loopback

operation holds this signal inactive.

DTR2 is multiplexed with CFG1 and BOUT2. DTR1 is multiplexed

with BADDR0 and BOUT1.

ERR

116

Parallel Port

Input

Group 3

Error – This input signal is set active low by the printer when it has

detected an error. This pin is internally connected to a nominal 25 K

Ω

pull-up resistor.

GPIO17-10

156-149

General

Purpose

I/O

Group 10

General Purpose I/O Signals 17-10 – General purpose I/O signals

of I/O Port 1.

GPIO17 is multiplexed with WDO.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

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PC97307 数据表(PDF) 17 Page - National Semiconductor (TI)

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