PC97338 datasheet(101/221 Pages) NSC

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3.6.7

The MODE Command

This command selects the special features of the con-

troller. The bits in the command bytes of the MODE

command are set to their default values after a hard-

ware reset.

Command Phase

Second Command Phase Byte

Bit 0 - Extended Track Range (ETR)

This bit determines how the track number is

stored. It is cleared to 0 after a software reset.

0 - Track number is stored as a standard 8-bit

value compatible with the IBM, ISO, and

Toshiba Perpendicular formats.

This allows access of up to 256 tracks during

a seek operation. (Default)

1 - Track number is stored as a 12-bit value.

The upper four bits of the track value are

stored in the upper four bits of the head num-

ber in the sector address field.

This allows access of up to 4096 tracks during

a seek operation. With this bit set, an extra

byte is required in the SEEK command phase

and SENSE INTERRUPT result phase.

Bits 3,2 - Low-Power Mode (LOW PWR)

These bits determine whether or not the FDC pow-

ers down and, if it does, they specific how long it

will take.

These bits disable power down, i.e., are cleared to

0, after a software reset.

00 - Disables power down. (Default)

01 - Automatic power down.

At a 500 Kbps data transfer rate, the FDC will

go into low-power mode 512 msec after it be-

comes idle.

At a 250 Kbps data transfer rate, the FDC will

go into low-power mode 1 second after it be-

comes idle.

10 - Manual power down.

The FDC powers down mode immediately.

11 - Not used.

Bit 5 - Implied Seek (IPS)

This bit determines whether the Implied Seek

(IPS) bit in a command phase byte of a read, write,

scan, or verify command is ignored or READ.

A software reset clears this bit to its default value

of 0.

0 - The IPS bit in the command byte of a read,

write, scan, or verify is ignored. (Default)

Implied seeks can still be enabled by the En-

able Implied Seeks (EIS) bit (bit 6 of the third

command phase byte) in the CONFIGURE

command.

1 - The IPS bit in the command byte of a read,

write, scan, or verify is read.

If it is set to 1, the controller performs seek

and sense interrupt operations before execut-

ing the command.

Bit 6 - Index Address Format (IAF)

This bit determines whether the controller formats

tracks with or without an index address field.

A software reset clears this bit to its default value

of 0.

0 - The controller formats tracks with an index ad-

dress field. (IBM and Toshiba Perpendicular

format).

1 - The controller formats tracks without an index

address field. (ISO format).

Bit 7 - Motor Timer Values (TMR)

This bit determines which group of values to use to

calculate the Delay Before Processing and Delay

After Processing times. The value of each is pro-

grammed using the SPECIFY command, which is

described on page 116 and in Tables 58 and 59.

A software reset clears this bit to its default value

of 0.

0 - Use the TMR = 0 group of values. (Default)

1 - Use the TMR = 1 group of values.

Third Command Phase Byte

Bit 4 - RECALIBRATE Step Pulses (R255)

This bit determines the maximum number of

RECALIBRATE step pulses the controller issues

before terminating with an error, depending on the

value of the Extended Track Range (ETR) bit, i.e.,

bit 0 of the second command phase byte in the

MODE command.

A software reset clears this bit to its default value

of 0.

0 - If ETR (bit 0) = 0, the controller issues a maxi-

mum of 85 recalibration step pulses.

7654

3210

0000

0001

TMR

IAF

IPS

LOW PWR

ETR

FWR FRD

BST R255

0000

DENSEL

BFR WLD

Head Settle Factor

0000

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