PC97338 datasheet(102/221 Pages) NSC

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If ETR (bit 0) = 1, the controller issues a maxi-

mum of 3925 recalibration step pulses. (De-

fault)

1 - If ETR (bit 0) = 0, the controller issues a maxi-

mum of 255 recalibration step pulses.

If ETR (bit 0) = 1, the controller issues a maxi-

mum of 4095 recalibration step pulses.

Bit 5 - Burst Mode Disable (BST)

This bit enables or disables burst mode, if the

FIFO is enabled (bit 5 in the CONFIGURE com-

mand is 0). If the FIFO is not enabled in the CON-

FIGURE command, then the value of this bit is

ignored.

A software reset enables burst mode, i.e., clears

this bit to its default value of 0, if the LOCK bit (bit

7 of the opcode of the LOCK command) is 0. If it is

1, BST retains its value after a software reset.

0 - Burst mode enabled for FIFO execution phase

data transfers. (Default)

1 - Burst mode disabled.

The FDC issues one DRQ or IRQ6 pulse for

each byte to be transferred while the FIFO is

enabled.

Bit 6 - FIFO Read Disable (FRD)

This bit enables or disables the FIFO for micropro-

cessor read transfers from the controller, if the

FIFO is enabled (bit 5 in the CONFIGURE com-

mand is 0). If the FIFO is not enabled in the CON-

FIGURE command, then the value of this bit is

ignored.

A software reset enables the FIFO for reads, i.e.,

clears this bit to its default value of 0, if the LOCK

bit (bit 7 of the opcode of the LOCK command) is

0. If it is 1, FRD retains its value after a software

reset.

0 - Enable FIFO. Execution phase of micropro-

cessor read transfers use the internal FIFO.

(Default)

1 - Disable FIFO. All read data transfers take

place without the FIFO.

Bit 7 - FIFO Write Enable or Disable (FWR)

This bit enables or disables write transfers to the

controller, if the FIFO is enabled (bit 5 in the CON-

FIGURE command is 0). If the FIFO is not enabled

in the CONFIGURE command, then the value of

this bit is ignored.

A software reset enables the FIFO for writes, i.e.,

clears this bit to its default value of 0, if the LOCK

bit (bit 7 of the opcode of the LOCK command) is

0. If it is 1, FWR retains its value after a software

reset.

0 - Enable FIFO. Execution phase microproces-

sor write transfers use the internal FIFO. (De-

fault)

1 - Disable FIFO. All write data transfers take

place without the FIFO.

Fourth Command Phase Byte

Bits 3-0 - Head Settle Factor

This field is used to specify the maximum time al-

lowed for the read/write head to settle after a seek

during an implied seek operation.

The value specified by these bits (the head settle

factor) is multiplied by the multiplier for selected

data rate to specify a head settle time that is within

the range for that data rate.

Use the following formula to determine the head

settle factor that these bits should specify:

Head Settle Factor x Multiplier = Head Settle Time

Table 47 shows the multipliers and head settle

time ranges for each data transfer rate.

The default head settle factor, i.e., value for these

bits, is 8.

TABLE 47. Multipliers and Head Settle Time

Ranges for Different Data Transfer Rates

Bit 4 - Scan Wild Card (WLD)

This bit determines whether or not FF (hex) from

either the microprocessor or the disk will be recog-

nized during a scan command as a wildcard char-

acter.

0 - An FF (hex) from either the microprocessor or

the disk during a scan command is interpreted

as a wildcard character that always matches.

(Default)

1 - The scan commands do not recognize FF

(Hex) as a wildcard character.

Bit 5 - CMOS Disk Interface Buffer Enable (BFR)

This bit configures drive output signals.

0 - Drive output signals are configured as stan-

dard 4 mA push-pull output signals (40 mA

sink, 4 mA source). (Default)

1 - Drive output signals are configured as 40 mA

open-drain output signals.

Data Transfer

Rate (Kbps)

Multiplier

Head Settle

Time Range (msec)

250

0 - 120

300

6.666

0 - 100

500

0 - 60

1000

0 - 30

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