PC97338 datasheet(107/221 Pages) NSC

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If the track address differs, either the Wrong Track

bit (bit 4) or the Bad Track bit (bit 1) (if the track ad-

dress is FF hex) is set in result phase Status reg-

ister 2 (ST2). See Section 3.5.3 on page 90.

If the head number, sector number or bytes-per-

sector code did not match, the Missing Data bit (bit

2) is set in result phase Status register 1 (ST1).

If the Address Mark (AM) was not found, the Miss-

ing Address Mark bit (bit 0) is set in ST1.

Section 3.5.2 on page 89 describes the bits of

ST1.

• A CRC error was detected in the address field. In

this case the CRC Error bit (bit 5) is set in ST1.

Once the address field of the desired sector is found,

the controller waits for the data separator to find the

data field for that sector.

If the data field (normal or deleted) is not found within

the expected time, the controller terminates the oper-

ation, enters the result phase and sets bit 0 (Missing

Address Mark) in ST1.

If a deleted data mark is found, and Skip (SK) control

is set to 1 in the opcode command phase byte, the

controller skips this sector and searches for the next

sector address field as described above. The effect of

Skip Control (SK) on the READ DATA command is

summarized in Table 51.

TABLE 51. Skip Control Effect on READ DATA

Command

After finding the data field, the controller transfers

data bytes from the disk drive to the host until the

bytes-per-sector count has been reached, or until the

host terminates the operation by issuing the Terminal

Count (TC) signal, reaching the end of the track or re-

porting an overrun.

See also, Section “The Phases of FDC Commands”

on page 85.

The controller then generates a Cyclic Redundancy

Check (CRC) value for the sector and compares the

result with the CRC value at the end of the data field.

After reading the sector, the controller reads the next

logical sector unless one or more of the following ter-

mination conditions occurs:

• The DMA controller asserted the Terminal Count

(TC) signal to indicate that the operation terminat-

ed. The Interrupt Code (IC) bits (bits 7,6) in ST0

are set to normal termination (00). See page 89.

• The last sector address (of side 1, if the Multi-

Track enable bit (MT) was set to 1) was equal to

the End of Track sector number. The End of Track

bit (bit 7) in ST1 is set. The IC bits in ST0 are set

to abnormal termination (01). This is the expected

condition during non-DMA transfers.

• Overrun error. The Overrun bit (bit 4) in ST1 is set.

The Interrupt Code (IC) bits (bits 7,6) in ST0 are

set to abnormal termination (01). If the micropro-

cessor cannot service a transfer request in time,

the last correctly read byte is transferred.

• CRC error. CRC Error bit (bit 5) in ST1 and CRC

Error in Data Field bit (bit 5) in ST2, are set. The

Interrupt Code (IC) bits (bits 7,6) in ST0 are set to

abnormal termination (01).

If the Multi-Track (MT) bit was set in the opcode com-

mand byte, and the last sector of side 0 has been

transferred, the controller continues with side 1.

Result Phase

Upon terminating the execution phase of the READ

DATA command, the controller asserts IRQ6, indicat-

ing the beginning of the result phase. The micropro-

cessor must then read the result bytes from the FIFO.

The values that are read back in the result bytes are

shown in Table 52. If an error occurs, the result bytes

indicate the sector read when the error occurred.

Skip

Control

(SK)

Data

Type

Sector

Read?

Control

Mark Bit 6

of ST2

Result

0Normal

Normal

Termination

Deleted

No More

Sectors Read

1Normal

Normal

Termination

Deleted

Sector

Skipped

5432

Result Phase Status Register 0 (ST0)

Result Phase Status Register 1 (ST1)

Result Phase Status Register 2 (ST2)

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

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