DocID025575 Rev 3

5/26

LED6001

Pin function

26

Table 2. Pin description

No.

Pin

1

PWMI

Device enable and PWM dimming control input.

2FSW

Switching frequency setting. A resistor between this pin and SGND sets the

desired switching frequency. This pin is also used as synchronization input. If tied

high (e.g. connected to LDO3 pin) a 600 kHz switching frequency is set.

3XFAULT

Fault indicator, open-drain output. This pin is tied low by the device in case of

faulty condition. See Section 7.4 on page 20 for details.

4LDO3

3.3 V linear regulator output and device supply. Connect a 1

F (typ.) bypass

MLCC between this pin and SGND as close as possible to the chip.

5SGND

Signal ground. Return for analog circuitry. All setting components must refer to this

grounding pin.

6COMP

Boost controller loop compensation. A simple RC series must be connected

between this pin and SGND for proper loop compensation. See Section 7.2.3 on

page 14 for details.

7ADIM

Analog dimming control input. The current at the output is linearly controlled by the

voltage applied to this pin (0.3 V to 1.2 V). When the device is set to operate in

standalone mode, a partition of the LDO3 voltage must be applied to this pin

through a resistor divider.

8OVFB

Output overvoltage protection feedback input. Connect to the central tap of

a resistor divider at the output.

9

CSNS

Boost controller power switch current sensing input. Connect to the source of the

external power MOSFET for proper switch overcurrent protection.

10

PWMO

PWM dimming control output. This pin provides a PWM output signal (in phase

with the one applied to the PWMI pin) for direct control of a dimming N-channel

MOSFET.

11

PGND

Power ground. Return for the VDR linear regulator and the power switch gate

drivers. Also used as reference for the power MOSFET current sensing circuitry.

Connect to ground as close as possible to the quiet terminal of the power switch

sensing resistor.

12

GATE

Power switch gate driver output. Connect to the gate of the power MOSFET

through a small value resistor.

13

VDR

5 V linear regulator output and gate driver supply. Connect a 1

F (typ.) bypass

MLCC between this pin and PGND as close as possible to the chip.

14

VIN

Supply voltage input. Connect this pin to the supply power rail. A 1

F (typ.)

bypass MLCC must be connected between this pin and PGND as close as

possible to the chip.

15

VFBN

Output current differential sensing input, negative terminal. Connect to the hot

terminal (load side) of the high-side sensing resistor.

16

VFBP

Output current differential sensing input, positive terminal. Connect to the quiet

terminal (output capacitor side) of the high-side sensing resistor.

-TPAD

Thermal pad. Connect to a suitable ground plane area in order to ensure proper

heat dissipation. Electrically connected to PGND and SGND.