Functional pin description

STBC03

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DocID029927 Rev 2

added to prevent unwanted charging cycle from restarting.

6.15

SD

The shutdown pin. In battery mode (if no valid VBUS voltage is present) a logic high level

on this pin asserts the low power consumption mode. If SD is kept high when a pulse is

applied to WAKE-UP pin the device exits the shutdown condition for the duration of the

WAKE-UP pulse. In shutdown mode, the battery drain is then reduced to less than 50 nA. If

a valid VBUS voltage is present, the SD pin status has no effect and the device is always

out of the shutdown condition.

6.16

SW1_OA, SW1_OB, SW1_I, SW2_OA, SW2_OB, SW2_I

SPDT load switch pins. Both of SPDT load switches are controlled by the digital control

of 3 Ω. SPDT load switches

can be paralleled to reduce the series resistor as well as to increase the allowable flowing

current.

6.17

SW_SEL1 and SW_SEL2

SW_SEL1 and SW_SEL2 drive the SPDT switches according to the following table. They

should be connected to GND if not used.

Table 9: SW_SEL1, SW_SEL2 operation

INPUTS

OUTPUTS

SW_SEL 1

SW_SEL2

SW1_OA

SW1_OB

SW2_OA

SW2_OB

0

0

SW1_I

Hi-Z

SW2_I

Hi-Z

1

0

Hi-Z

SW1_I

SW2_I

Hi-Z

0

1

SW1_I

Hi-Z

Hi-Z

SW2_I

1

1

Hi-Z

SW1_I

Hi-Z

SW2_I