STCF05

Detailed description

Doc ID 15257 Rev 4

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by strobing the TRIG pin. Time-out counter will cumulate every flash on-time until the

defined time-out is reached, unless it is reloaded by updating the CMD_REG. After a single

or multiple flash operations are timed-out, the device automatically goes into ready mode by

resetting the TRIG_EN bit, and also resets the F_RUN bit. The ATN pin is pulled down to

inform the microprocessor that the STAT_REG has been updated.

10.5

External (microprocessor) temporization using TRIG_EN bit

Even if it is possible, it is not recommended to use the TRIG_EN bit to start and stop the

flash operation, because of I²C bus latencies: this would result in inaccurate flash timing.

Nevertheless, if this operation mode is chosen, the TRIG pin has to be kept High (logic level

or wired to VBAT), leaving the whole flash control to the I²C bus. Also in this operation mode

the time counter will time-out flash operation and keep the energy dissipated by the LED

within safe limits in case of SW deadlock.

10.6

Single flash using internal temporization

Flash triggering can be obtained either by TRIG pin (hard-triggering) or by I²C commands

(soft-triggering). The first solution is recommended for an accurate start time, while the

second is less accurate because of the I²C bus time latency. Stop time is defined by the

STCF05 internal temporization and its accuracy is determined by the internal oscillator. For

hard-triggering, it is necessary to set the TRIG_EN bit in advance. For soft-triggering, the

TRIG pin has to be kept High (logic level or wired to VBAT) and the flash can be started by

setting the FTIM and the TRIG_EN through I²C (both are located in the CMD REG). There is

a delay time between the moment the flash is triggered and when it appears. This delay is

caused by the time necessary to charge the output capacitor up, which is around 1.2 ms

depending on battery voltage and output current value. Once triggered, the flash operation

will be stopped when the time counter reaches zero. As soon as the flash is finished, the

F_RUN bit is reset, the ATN pin is pulled down for 11 µs to inform the microprocessor that

the STAT_REG has been updated and the device goes back to ready mode. If flash longer

than the internal timer allows or a continuous flash is necessary, the FTIM must be reloaded

through I²C bus every time, before the internal timer reaches zero. For example: To get a

continuous flash, set FTIM to 1.5 s and every 1 s reload the CMD_REG.

10.7

Multiple flash using internal temporization

This operation has to be processed as a sequence of single flashes using internal

temporization starting from hard or soft triggering. Since the TRIG_EN bit is reset at the end

of each flash, it is necessary to reload the CMD_REG to start the next one.