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TNETV2665ZWT4 数据表(PDF) 159 Page - Texas Instruments |
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TNETV2665ZWT4 数据表(HTML) 159 Page - Texas Instruments |
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159 / 249 page  MXI POR RESET RESETOUT SYSCLKREFCLK (PLLC1) SYSCLK1 SYSCLK2 SYSCLK3 CLKOUT0 Bootand ConfigurationPins Config PowerSuppliesStable 1 4 5 2 3 PLL1Clock Div1Clock Div3Clock Div6Clock DrivenorHi-Z 8 6 DrivenorHi-Z Z+/LowGroup (Zlonger-to-low) Z+/HighGroup (Zlonger-to-high) ZGroup 8 DDR2ZGroup DDR2LowGroup DDR2HighGroup Z/HighGroup (Z-to-high) 7 Z/LowGroup (Z-to-low) 7 DrivenorHi-Z DrivenorHi-Z DrivenorHi-Z 6 6 6 6 6 8 Z+/InvalidGroup (Zlonger-to-invalid) 9 Invalid TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 A. Pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. For more details on what pin group (e.g., Z Group, Z/Low Group, Z/High Group, etc.) each pin belongs to, see Section 6.5.8, Pin Behaviors at Reset. Figure 6-8. Warm Reset (RESET) Timing Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 159 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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