L9659 datasheet(21/51 Pages) STMICROELECTRONICS

21 / 51 page

L9659

Functional description

Doc ID 022048 Rev 2

21/51

3.3

Serial peripheral interface (SPI)

The L9659 contains one serial peripheral interfaces for control of the squib functions. The

following table shows features that are accessed/controlled by the SPI.

The software reset accessed over SPI will reset squib functions. The L9659 has a counter to

verify the number of clocks in SCLK. If the number of clocks in SCLK is not equal to 16

clocks while CS_D is asserted, it ignores the SPI message and sends a SPI fault response.

L9659 computes SPI error length flag through counting the number ofSCLK rising edges

occurring when CS_D is active. If the first SCLK rising edge occurs when CS_D is inactive

and the falling edge occurs when CS_D is low, it is considered as valid edge.

MOSI commands contain several bits not used, all those bits must be 0. Commands are not

recognized valid if one or more not used bits are not 0.

3.3.1

SPI pin descriptions

Chip select (CS_D)

Chip-select inputs select the L9659 for serial transfers. CS_D can be asserted at any given

time and are active low. When chip-select is asserted, the respective MISO pin is released

from tri-state mode, and all status information is latched into the SPI shift register. While

chip-select is asserted, register data is shifted into MOSI pin and shifted out of MISO pin on

each subsequent SCLK. When chip-select is negated, MISO pin is tri-stated. To allow

sufficient time to reload the registers; chip-select pin shall remain negated for at least tCSN.

The chip-select inputs have current sinks which pull these pins to the negated state when

there is an open circuit condition. These pins have TTL level compatible input voltages

allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.

Serial clock (SCLK)

SCLK input is the clock signal input for synchronization of serial data transfer. This pin has

TTL level compatible input voltages allowing proper operation with microprocessors using a

3.3 to 5.0 volt supply. When chip select is asserted, both the SPI master and L9659 will latch

input data on the rising edge of SCLK. The L9659 shifts data out on the falling edge of

SCLK.

Serial data output (MISO)

MISO output pins shall be in one tri-state condition when chip select is negated. When chip

select is asserted, the MSB is the first bit of the word/byte transmitted on MISO and the LSB

is the last bit of the word/byte transmitted. This pin supplies a rail to rail output, so if

interfaced to a microprocessor that is using a lower VDD supply, the appropriate

microprocessor input pin shall not sink more than IOH(min) and shall not clamp the MISO

output voltage to less than VOH(min) while MISO pin is in a logic “1” state. When connecting

to a micro using a lower supply, such as 3.3V, a resistor divider shall be used with high

enough impedance to prevent excess current flow.

Table 9.

Features that are accessed/controlled for the SPI

Function

Pin names

Features accessed

Squib diagnostic and deployment SPI

SCLK

MISO

MOSI

CS_D

All Squib Diagnostics; Squib

related status information;

Squib Arming and Firing;

Software Reset; Component

ID & Revision

L9659 数据表(PDF) 21 Page - STMicroelectronics

L9659 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

数据表下载