TNETV2666FIBZWT datasheet(173/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

6.9.3

EMIFA Electrical Data/Timing

Table 6-24. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)

(see Figure 6-14 and Figure 6-15)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

NOM

MAX

READS and WRITES

tw(EM_WAIT)

Pulse duration, EM_WAIT assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[15:0] valid before EM_OE high

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

tsu

Setup time, EM_WAIT asserted before EM_OE high(2)

4E + 5

(EMWAIT-EMOEH)

WRITES

su(EMWAIT-

Setup time, EM_WAIT asserted before EM_WE high(2)

4E + 5

EMWEH)

(1)

E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 600 MHz, use E = 10 ns.

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended

wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Peripheral Information and Electrical Specifications

173

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