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TNETV2666FIBZWT 数据表(PDF) 174 Page - Texas Instruments

部件名 TNETV2666FIBZWT
功能描述  Fixed-Point Digital Signal Processor
PDF  249 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2666FIBZWT 数据表(HTML) 174 Page - Texas Instruments

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TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
www.ti.com
Table 6-25. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module(1) (2) (see Figure 6-14 and Figure 6-15)
-7/-6/-5/-4
NO
-L/-Q6/-Q5/-Q4
PARAMETER
UNIT
.
MIN
NOM
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA + 1) * E
ns
READS
(RS + RST + RH +
3
tc(EMRCYCLE)
EMIF read cycle time
ns
TA + 4) * E(3)
Output setup time, EM_CS[5:2] low to
(RS + 1) * E - 4
(RS + 1) * E + 4
ns
EM_OE low (SS = 0)
4
tsu(EMCSL-EMOEL)
Output setup time, EM_CS[5:2] low to
-4
4
ns
EM_OE low (SS = 1)
Output hold time, EM_OE high to
(RH + 1) * E - 4
(RH + 1) * E + 4
ns
EM_CS[5:2] high (SS = 0)
5
th(EMOEH-EMCSH)
Output hold time, EM_OE high to
-4
4
ns
EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to
6
tsu(EMBAV-EMOEL)
(RS + 1) * E - 4
(RS + 1) * E + 4
ns
EM_OE low
Output hold time, EM_OE high to
7
th(EMOEH-EMBAIV)
(RH + 1) * E - 4
(RH + 1) * E + 4
ns
EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to
8
tsu(EMBAV-EMOEL)
(RS + 1) * E - 4
(RS + 1) * E + 4
ns
EM_OE low
Output hold time, EM_OE high to
9
th(EMOEH-EMBAIV)
(RH + 1) * E - 4
(RH + 1) * E + 4
ns
EM_A[21:0] invalid
10
tw(EMOEL)
EM_OE active low width
(RST + 1) * E(3)
ns
Delay time from EM_WAIT deasserted
11
td(EMWAITH-EMOEH)
4E + 4
ns
to EM_OE high
WRITES
(WS + WST + WH +
15
tc(EMWCYCLE)
EMIF write cycle time
ns
TA + 4) * E(3)
Output setup time, EM_CS[5:2] low to
(WS + 1) * E - 4
(WS + 1) * E + 4
ns
EM_WE low (SS = 0)
16
tsu(EMCSL-EMWEL)
Output setup time, EM_CS[5:2] low to
-4
4
ns
EM_WE low (SS = 1)
Output hold time, EM_WE high to
(WH + 1) * E - 4
(WH + 1) * E + 4
ns
EM_CS[5:2] high (SS = 0)
17
th(EMWEH-EMCSH)
Output hold time, EM_WE high to
-4
4
ns
EM_CS[5:2] high (SS = 1)
Output setup time, EM_R/W valid to
18
tsu(EMRNW-EMWEL)
(WS + 1) * E - 4
(WS + 1) * E + 4
ns
EM_WE low
Output hold time, EM_WE high to
19
th(EMWEH-EMRNW)
(WH + 1) * E - 4
(WH + 1) * E + 4
ns
EM_R/W invalid
Output setup time, EM_BA[1:0] valid to
20
tsu(EMBAV-EMWEL)
(WS + 1) * E - 4
(WS + 1) * E + 4
ns
EM_WE low
Output hold time, EM_WE high to
21
th(EMWEH-EMBAIV)
(WH + 1) * E - 4
(WH + 1) * E + 4
ns
EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to
22
tsu(EMAV-EMWEL)
(WS + 1) * E - 4
(WS + 1) * E + 4
ns
EM_WE low
Output hold time, EM_WE high to
23
th(EMWEH-EMAIV)
(WH + 1) * E - 4
(WH + 1) * E + 4
ns
EM_A[21:0] invalid
(1)
RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STrobe, WH = Write Hold, TA = Turn
Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous n Configuration
and Asynchronous Wait Cycle Configuration Registers.
(2)
E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 600 MHz, use E = 10 ns.
(3)
When EW = 1, the EMIF will extend the strobe period up to 4,096 additional cycles when the EM_WAIT pin is asserted by the external
device.
174
Peripheral Information and Electrical Specifications
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320C6424



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