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TNETV2666FIBZWT 数据表(PDF) 178 Page - Texas Instruments |
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TNETV2666FIBZWT 数据表(HTML) 178 Page - Texas Instruments |
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178 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com 6.9.4 DDR2 Memory Controller The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM devices. For details on the DDR2 Memory Controller, see the TMS320C642x DSP Peripherals Overview Reference Guide (literature number SPRUEM3) and the TMS320C642x DSP DDR2 Memory Controller User's Guide (literature number SPRUEM4). A memory map of the DDR2 Memory Controller registers is shown in Table 6-26. Table 6-26. DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C4 004C DDRVTPER DDR2 VTP Enable Register 0x01C4 2038 DDRVTPR DDR2 VTP Register 0x2000 0000 - 0x2000 0003 - Reserved 0x2000 0004 SDRSTAT SDRAM Status Register 0x2000 0008 SDBCR SDRAM Bank Configuration Register 0x2000 000C SDRCR SDRAM Refresh Control Register 0x2000 0010 SDTIMR SDRAM Timing Register 0x2000 0014 SDTIMR2 SDRAM Timing Register 2 0x2000 0020 PBBPR Peripheral Bus Burst Priority Register 0x2000 0024 - 0x2000 00BF - Reserved 0x2000 00C0 IRR Interrupt Raw Register 0x2000 00C4 IMR Interrupt Masked Register 0x2000 00C8 IMSR Interrupt Mask Set Register 0x2000 00CC IMCR Interrupt Mask Clear Register 0x2000 00D0 - 0x2000 00E3 - Reserved 0x2000 00E4 DDRPHYCR DDR PHY Control Register 0x2000 00E8 - 0x2000 00EF - Reserved 0x2000 00F0 VTPIOCR DDR VTP IO Control Register 0x2000 00E8 - 0x2000 7FFF - Reserved 178 Peripheral Information and Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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