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STM6321 数据表(PDF) 10 Page - STMicroelectronics |
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STM6321 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 31 page ![]() Operation STM632x, STM682x 10/31 DocID11110 Rev 13 2 Operation 2.1 Reset output The STM6xxx supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog timeout occurs, or when the push-button reset input (MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1 V for TA = 0 to 85 °C. During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low for the reset timeout period, trec. After this interval reset is de-asserted. Each time RST is asserted, it stays low for at least the reset timeout period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. 2.2 Open drain RST output The STM6321/6322/6822 have an active low, open drain reset output. This output structure will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic low, and small enough to register a logic high while supplying all input current and leakage paths connected to the reset output line. A 10 k Ω pull-up resistor is sufficient in most applications. Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies 1. STM6322/6822. 2. STM6321/6822. 3. STM6321/6322. |
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