TNETV2685FIBZUTA7 datasheet(3/191 Pages) TI1

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-

integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; four 64-

bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit

or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable

interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless

external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for

slower memories/peripherals, and a higher DDR2 SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices.

The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,

BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display

modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is

splittable between the two channels.

For more details on the video port peripherals, see the TMS320DM647/DM648 Video Port User's Guide

(literature number SPRUEM1).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to

enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with

host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

The devices have a complete set of development tools. These include C compilers, a DSP assembly

optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into

source code execution.

Features

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