TNETV2685FIBZUTA7 datasheet(68/191 Pages) TI1

68 / 191 page

CLKIN

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

6.4.4

PLL1 Controller Input and Output Clock Electrical Data/Timing

Table 6-8. Timing Requirements for CLKIN1(1)(2) (see Figure 6-6)

720, 800, 900, 1100

NO.

PLL MODES(3)

UNIT

MIN

MAX

tc(CLKIN1)

Cycle time, CLKIN1

tw(CLKIN1H)

Pulse duration, CLKIN1 high

0.4C

tw(CLKIN1L)

Pulse duration, CLKIN1 low

0.4C

tt(CLKIN1)

Transition time, CLKIN1

1.2

tJ(CLKIN1)

Period jitter, (peak-to-peak), CLKIN1

100

(1)

The reference points for the rise and fall transitions are measured at 3.3-V VIL MAX and VIH MIN.

(2)

C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

(3)

The PLL1 multiplier factors (x1 [BYPASS], x16 to x32) further limit the MIN and MAX values for tc(CLKIN1). See Section 6.3.5 for

supported PLL1 multiplier factors.

Figure 6-6. CLKIN1 Timing

6.4.5

PLL1 Controller Register Description(s)

A summary of the PLL1 controller registers is shown in Table 6-9.

Table 6-9. PLL1 and Reset Controller Registers Memory Map

HEX ADDRESS RANGE

DESCRIPTION

0x020E 0000

PID

Peripheral Identification and Revision Information Register

0x020E 00E4

RSTYPE

Reset Type Register

0x020E 0100

PLLCTL

PLL Controller 1 Operations Control Register

0x020E 0110

PLLM

PLL Controller 1 Multiplier Control Register

0x020E 0114

PREDIV

PLL Pre-Divider Control Register

0x020E 011C

PLLDIV2

PLL Controller 1 Control-Divider 2 Register (SYSCLK2)

0x020E 0138

PLLCMD

PLL Controller 1 Command Register

0x020E 013C

PLLSTAT

PLL Controller 1 Status Register (Shows PLLC1 Status)

0x020E 0140

ALNCTL

PLL Controller Clock Align Control Register

0x020E 0144

DCHANGE

PLLDIV Ratio Change Status Register

0x020E 0150

SYSTAT

PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off

Status)

0x020E 0160

PLLDIV4

PLL Controller 1 Control-Divider 4 Register (SYSCLK4)

Peripheral Information and Electrical Specifications

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