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TNETV2685FIDZUT5 数据表(PDF) 45 Page - Texas Instruments

部件名 TNETV2685FIDZUT5
功能描述  Digital Media Processor
PDF  191 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2685FIDZUT5 数据表(HTML) 45 Page - Texas Instruments

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TMS320DM647
TMS320DM648
www.ti.com
SPRS372H – MAY 2007 – REVISED APRIL 2012
Table 3-7. PINMUX Register Field Descriptions (continued)
Bit
Field
Value
Description
15:14
VP34_EN
Controls the pin muxing between Video Port 3-4 and EMIFA (6)
UNMUXED(7)
MUXED(8)
VP4D05/VP4CLK1
VP3/VP4
EMIFA
00
3-state
3-state
01
3-state
3-state
10
Disable
EMIFA
11
Enable
VP3/VP4
13:12
SPI_UART_EN
Controls the pin muxing between SPI and UART
UNMUXED (9)
MUXED (10)
SPICLK
SPI or UART
00
3-state
3-state
01
Enable
SPI
10
Disable
UART
11
Enable
SPIDI
SPIDO
UART_TX
UART_RX
11:10
Reserved
Reserved
(6)
The value of VP34_EN depends on the BOOTMODE[3:0] pin value at reset. If the BOOTMODE[3:0] is 0100, the VP3/4 and the EMIFA
mux defaults to EMIFA enable (the value is 10b).
(7)
The complete list of pins: K1, M6.
(8)
The complete list of pins: T1, P1, T2, R1, P2, T6, T5, T4, T3, R6, R5, R4, R3, R2, P6, P5, P4, P3, N4, N6, N5, L1, J2, J1, K2, L2, M4,
M5, L3, L4, L5, K3, K4, L6, K5, J3, J4, J5, J6, K6.
(9)
The complete list of pin:F22
(10) The complete list of pins: D23, F23, G23, F21
Copyright © 2007–2012, Texas Instruments Incorporated
Device Configuration
45
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Product Folder Link(s): TMS320DM647 TMS320DM648



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