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TNETV2685FIDZUT5 数据表(PDF) 47 Page - Texas Instruments |
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TNETV2685FIDZUT5 数据表(HTML) 47 Page - Texas Instruments |
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47 / 191 page  TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 Table 3-8. PCI/UHPI/GPIO Block: PCI MUXed With UHPI and GPIO[0:7] MUXED(1) PCI UHPI/GPIO[0:7] UHPIEN (pin) 1 UHPI/GPIO[0:7] 0 PCI (1) The complete list of pin:AA22, AB22, AC21, AA23, AC22, AB21, AA21, Y21, AB20, AA20, Y20, Y19, AB18, AA19, AC18, AA18, Y16, AB15, AA15, Y15, W15, V15, AC14, AB14, W14, V14, AC13, AB13, AA13, Y13 , W13, V13, W19, Y18, Y17, W17, W18, AC20, AC17, W16, Y14, AC15, AA16, AB17, U13, U12, V12, AA12, AA17, AA14. For information on the Ethernet Subsystem registers, see the TMS320DM647/DM648 DSP Subsystem Reference Guide (literature number SPRUEU6). 3.2.7 MAC Address Registers • MAC_ADDR_R0 • MAC_ADDR_R1 • MAC_ADDR_RW0 • MAC_ADDR_RW1 Two sets of registers provide default MAC addresses for the device. One set - MAC_ADDR_R0 and MAC_ADDR_R1 - is read only and the other set - MAC_ADDR_RW0 and MAC_ADDR_RW1 - includes read and write registers. Figure 3-7. MAC_ADDR_R0 Register 31 0 MAC_ID R-MAC ADDRESS[31:0] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-9. MAC_ADDR_R0 Register Field Descriptions Bit Field Value Description 31:0 MAC_ID Mac Bit 0 of MAC_ID is bit 0 of MAC Address Address[31:0] of the device Figure 3-8. MAC_ADDR_R1 Register 31 24 23 16 CRC Reserved R-CRC for the MAC_ID R-00000000 15 0 MAC_ID R-MAC ADDRESS[47:32] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-10. MAC_ADDR_R1 Register Field Descriptions Bit Field Value Description 31:24 CRC CRC of the MAC This field will hold the CRC of the MAC address of that particular device. ID 23:16 Reserved 0x00 Reserved Copyright © 2007–2012, Texas Instruments Incorporated Device Configuration 47 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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