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L6732C

6 Application details

23/32

6.4

Compensation network

The loop is based on a voltage mode control (Figure 15.). The output voltage is regulated to the

internal/external reference voltage and scaled by the external resistor divider. The error

and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is

closed loop transfer function with the highest 0dB crossing frequency to have fastest transient

response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the

load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade

slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation

networks, the following suggestions may be used:

●

Modulator singularity frequencies:

●

Compensation network singularity frequencies:

Figure 15. Compensation network

Cout

L

LC

⋅

=

1

ω

Cout

ESR

ESR

⋅

=

1

ω

(13)

(14)

⎟⎟⎠

⎞

⎜⎜⎝

⎛

+

⋅

⋅

=

19

18

19

18

5

1

1

C

C

C

C

R

P

ω

20

4

2

1

C

R

P

⋅

=

ω

(15)

(16)

19

5

1

1

C

R

Z

⋅

=

ω

()

4

3

20

2

1

R

R

C

Z

+

⋅

=

ω

(17)

(18)

Obsolete

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- Obsolete

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