VSC7212RG datasheet(30/34 Pages) VITESSE

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ESE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

Page 30

G52268-0, Rev 3.3

04/10/01

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

ERR

TTL

ERRor Detect. When HIGH, an invalid 10-bit character or disparity error

has been detected and the data on R(7:0) is invalid.

When ENDEC=LOW, this is equivalent to data bit R9.

RCLK

RCLKN

TTL

Recovered CLocK Outputs. These outputs are driven from the recovered

clock, at 1/10 or 1/20 the baud rate, as selected by RMODE(1:0) and

DUAL. When unused, RCLK is HIGH and RCLKN is LOW.

RMODE0

RMODE1

TTL

Receive Output Data Timing MODE. Determines the timing reference for

R(7:0), IDLE, KCH, ERR, PSDET, RSDET and TBERR, as defined in

Table 5.

PRX+

PRX-

IPECL

Primary Differential Serial RX Inputs. These pins receive the serialized

input data when LBEN(1) is LOW and RXP/R is HIGH, otherwise they are

unused. They are internally biased at VDD/2 through a 3.2KW resistor to the

bias voltage. AC coupling is recommended.

RRX+

RRX-

IPECL

Redundant Differential Serial RX Inputs. These pins receive the serialized

input data when LBEN(1) is LOW and RXP/R is LOW, otherwise they are

unused. They are internally biased at VDD/2 through a 3.2KW resistor to the

bias voltage. AC coupling is recommended.

LBEN0

LBEN1

TTL

Loop Back ENable. These inputs control serial or parallel loopback

configuration as described in Table 8.

RXP/R

TTL

RX Input Primary/Redundant serial input select. When LBEN(1) is LOW,

this input selects PRX+/- as the serial input source when HIGH and RRX+/-

as the serial input source when LOW.

PSDET

TTL

Primary Analog Signal DETect. This output goes HIGH when the

amplitude on PRX is greater than 200mV and LOW when the input is less

than 100mV. PSDET is not defined when the input is between 100mV and

200mV. Output timing is same as R(7:0).

RSDET

TTL

Redundant Analog Signal DETect. This output goes HIGH when the

amplitude on RRX is greater than 200mV, LOW when the input is less than

100 mV. RSDET is not defined when the input is between 100mV and

200mV. Output timing is same as R(7:0).

REFCLKP

REFCLKN

IPECL

REFCLK Differential Positive and Negative PECL or Single-Ended TTL

Inputs. This rising edge of this clock latches transmit data and control into

the input register. It also provides the reference clock, at 1/10th or 1/20th of

the baud rate to the PLL as selected by DUAL. If TTL, connect to

REFCLKP but leave REFCLKN open. If PECL, connect both REFCLKP

and REFCLKN.

REFOUT

TTL

REFerence Clock OUTput: This is an output from the clock synthesizer at

the baud rate divided by ten.

CAP0

CAP1

AAnalog

Loop Filter CAPacitor for Clock Generation PLL. Nominally 0.1 µF,

amplitude is less than 3V. See the Loop Filter Applications section for more

details.

DUAL

TTL

DUAL Clock Mode. When LOW, REFCLK and RCLK/RCLKN are 1/10th

the baud rate. When HIGH, they are 1/20th the baud rate.

Name

I/O

Type

Pin Description

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VSC7212RG 数据表(PDF) 30 Page - Vitesse Semiconductor Corporation

VSC7212RG 数据表(HTML) 30 Page - Vitesse Semiconductor Corporation

Html Pages

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数据表 下载

链接网址

数据表下载