Pin configuration

STEF033

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DocID025099 Rev 2

2

Pin configuration

Figure 2. Pin configuration (top view)

Table 1. Pin description

Pin n°

(DFN)

Pin n°

(Flip Chip)

Symbol

Note

1,2,3,4,5

C1,C2,C3

Connected to the source of the internal power MOSFET and to the

output terminal of the fuse

6

N.C.

I-lim -

A resistor between these two pins sets the overload and short-circuit

current limit levels. On the Flip Chip the resistor must be connected

between the I-Lim+ and Source pins

7A1

I-lim +

8A2

En/Fault

The Enable/Fault pin is a tri-state, bi-directional interface. During normal

operation the pin must be left floating, or it can be used to disable the

output of the device by pulling it to ground using an open drain or open

collector device. If a thermal fault occurs, the voltage on this pin goes

into an intermediate state to signal a monitor circuit that the device is in

thermal shutdown. It can be connected to another device of this family to

cause a simultaneous shutdown during thermal events.

9N.C.

dv/dt

The internal dv/dt circuit controls the slew rate of the output voltage at

turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms.

An external capacitor can be added to this pin to increase the ramp time.

If an additional capacitor is not required, this pin should be left open.

This feature is not available on the Flip Chip version.

10

A3

GND

Ground pin

Exposed

pad

B1,B2,B3