General description

VIPer0P

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DocID028423 Rev 2

During the on-time, the inductor is charged through the input voltage and if it cannot be

discharged by the same amount during the off-time, in every switching cycle there is a net

increase of the average inductor current, that can reach dangerously high values until the

output capacitor is not charged enough to ensure the inductor discharge rate needed for

the volt-second balance. This condition is common at converter startup, because of the low

output voltage.

In the following Figure 28: "Pulse skipping during start-up for FOSC = 60 kHz" the effect of

pulse skipping feature on the DRAIN peak current shape is shown (solid line), compared

with the DRAIN peak current shape when pulse skipping feature is not implemented

(dashed line). Providing more time for cycle-by-cycle inductor discharge when needed, this

feature is effective in keeping low the maximum DRAIN peak current avoiding the flux

runaway condition.

4.8

Direct feedback

The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground

reference and output are FB, EAGND and COMP, respectively. The internal reference

topologies this makes it possible to tightly regulate positive output voltages through a

simple voltage divider applied among the output voltage terminal, FB and EAGND, and

soldering SGND to EAGND. Since EAGND can float down to -12.5 V with respect to the

ground of the IC (SGND), negative output voltages can be regulated as well, connecting

EAGND to the negative rail, and the voltage divider among FB, EAGND and SGND, as

shown in Figure 34: "Negative output flyback converter (non-isolated)".

The E/A output is scaled down and fed into the PWM comparator, where it is compared to

the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by-

cycle drain current limitation.

An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the

overall control loop.