LNBH26L

I²C bus interface

Doc ID 022876 Rev 1

13/28

6

I²C bus interface

Data transmission from the main microprocessor to the LNBH26L, and vice versa, takes

place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up

resistors to positive supply voltage must be externally connected).

6.1

Data validity

As shown in

Figure 7, the data on the SDA line must be stable during the high semi-period

of the clock. The high and low state of the data line can only change when the clock signal

on the SCL line is LOW.

6.2

START and STOP condition

As shown in

Figure 8, a START condition is a high to low transition of the SDA line while

SCL is HIGH. The STOP condition is a low to high transition of the SDA line while SCL is

HIGH. A STOP condition must be sent before each START condition.

6.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSb is transferred first.

6.4

Acknowledge

The master (microprocessor) puts a resistive high level on the SDA line during the

acknowledge clock pulse (see

Figure 9). The peripheral (LNBH26L) which acknowledges

must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA

line is stable low during this clock pulse. The peripheral which has been addressed must

generate an acknowledge after the reception of each byte, otherwise the SDA line remains

at the high level during the ninth clock pulse time. In this case the master transmitter can

generate the STOP information in order to abort the transfer. The LNBH26L won't generate

6.5

Transmission without acknowledge

If the detection of LNBH26L acknowledge is not necessary, the microprocessor can use a

simpler transmission; it simply waits one clock without checking the slave acknowledging,

and sends the new data. This approach is of course less protected from misworking and

decreases noise immunity.