LNBH26L

I²C interface protocol

Doc ID 022876 Rev 1

19/28

7.4

Status registers

The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic

functions described in the following tables.

N/A = Reserved bit.

All bits reset to “0” at power-on.

N/A = Reserved bit.

All bits reset to “0” at power-on.

Table 10.

STATUS 1 (read register. Register address = 0X0)

Bit

Name

CH

Value

Description

Bit 0

(LSb)

OLF-A

A

1

for the overload operation and PCL settings.

0

Bit 1

OLF-B

B

1

for the overload operation and PCL settings.

0

Bit 2

N/A

-

-

Reserved

Bit 3

N/A

-

-

Reserved

Bit 4

N/A

-

-

Reserved

Bit 5

N/A

-

-

Reserved

Bit 6

OTF

A/B

1

setting in

Table 9.

0

protection threshold.

Bit 7

(MSb)

PNG

A/B

1

0

Table 11.

STATUS 2 (read register. Register address = 0X1)

Bit

Name

CH

Value

Description

Bit 0

(LSb)

N/A

-

-

Reserved

Bit 1

N/A

-

-

Reserved

Bit 2

N/A

-

-

Reserved

Bit 3

N/A

-

-

Reserved

Bit 4

N/A

-

-

Reserved

Bit 5

N/A

-

-

Reserved

Bit 6

N/A

-

-

Reserved

Bit 7

(MSb)

N/A

-

-

Reserved