SPC564A80L7 datasheet(23/157 Pages) STMICROELECTRONICS

23 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

23/157

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Saturated or non-saturated modes

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Programmable Rounding (Convergent; Two’s Complement; Truncated)

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Prefill mode to precondition the filter before the sample window opens

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Supports Multiple Cascading Decimation Filters to implement more complex filter

designs

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Optional Absolute Integrators on the output of Decimation Filters

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Full duplex synchronous serial interface to an external device

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Free-running clock for use by an external device

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Supports a 26-bit message length

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Priority based queues

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Supports six queues with fixed priority. When commands of distinct queues are

bound for the same ADC, the higher priority queue is always served first

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Queue_0 can bypass all prioritization, buffering and abort current conversions to

start a Queue_0 conversion a deterministic time after the queue trigger

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Supports software and hardware trigger modes to arm a particular queue

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Generates interrupt when command coherency is not achieved

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External hardware triggers

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Supports rising edge, falling edge, high level and low level triggers

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Supports configurable digital filter

1.5.14

DSPI

The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface

for communication between the SPC564A80 MCU and external devices. The DSPI supports

pin count reduction through serialization and deserialization of eTPU and eMIOS channels

and memory-mapped registers. The channels and register content are transmitted using a

SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and

phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to

serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be

configured to serialize data to an external device that implements the Microsecond Bus

protocol. There are three identical DSPI blocks on the SPC564A80 MCU. The DSPI pins

support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed

operation.

DSPI module features include:

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Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and

DSPI_C

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3 sources of serialized data: eTPU_A, eMIOS output channels and memory-mapped

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4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external

Interrupt input request, memory-mapped register in the DSPI

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32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the

SIU to select either GPIO, eTPU or eMIOS bits for serialization

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The DSPI Module can generate and check parity in a serial frame

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