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STM8SPLNB1 数据表(PDF) 25 Page - STMicroelectronics |
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STM8SPLNB1 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 44 page  DocID018831 Rev 5 25/44 STM8SPLNB1 Electrical characteristics 43 4.3.4 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. The reset network shown in the following Figure 12. protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in the Table 26.: RESET pin characteristics. Otherwise the reset is not taken into account internally. Figure 12. Recommended reset pin protection Table 26. RESET pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(RST) RESET Input low level voltage (1) 1. Data based on characterization results, not tested in production. - -0.3 V 0.3 x VDD V VIH(RST) RESET Input high level voltage (1) - 0.7 x VDD VDD + 0.3 RPU(RST) RESET Pull-up resistor (2) 2. The RPU pull-up equivalent resistor is based on a resistive transistor. -30 55 80 k |
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