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STM32F732ICK6 数据表(PDF) 25 Page - STMicroelectronics |
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STM32F732ICK6 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 122 page  DocID028480 Rev 1 25/122 STM32F732xx STM32F733xx Functional overview 44 Figure 9. Power supply supervisor interconnection with internal reset OFF The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 10). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry must be disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. Figure 10. PDR_ON control with internal reset OFF |
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