Connection Diagrams

Plastic Chip Carrier (PCC) Package

TLH5118 – 5

Order Number TP3155V

See NS Package Number V20A

Dual-In-Line Package

TLH5118 – 6

Top View

Order Number TP3155N

See NS Package Number N20A

Pin Descriptions

Symbol

Description

A conventional CMOS frame sync output

which is normally low and goes active-high

for 8 cycles of BCLK when a valid transmit

time slot assignment is made

A conventional CMOS frame sync output

which is normally low and goes active-high

for 8 cycles of BCLK when a valid receive

time slot assignment is made

A transmit frame sync output similar to pin 1

A receive frame sync output similar to pin 2

An open-drain N-channel output which is nor-

mally high impedance but pulls low during any

active transmit time slot

The input for an 8-bit serial control word X is

the first bit clocked in

The clock input for the control interface

CS

The active-low chip select for the control in-

terface

MODE

The mode select input When left open-circuit

when connected to GND mode 2 is selected

GND

The 0V ground connection to the device

Symbol

Description

BCLK

The bit clock input which should run at the

same rate as that for the COMBO CODEC

Filter COMBO

XSYNC

The transmit TS0 sync pulse input Must be

synchronous with BCLK

RSYNCCH2 The function of this input is determined by the

MODE input (pin 9) In mode 1 this is the re-

ceive TS0 sync pulse RSYNC which must be

synchronous with BCLK In mode 2 this is the

CH2 input for the MSB of the channel select

word

CH1

The input for the next significant bit of the

channel select word

CH0

The input for the LSB of the channel select

word which defines the frame sync output af-

fected by the following control word

A transmit frame sync output similar to pin 1

A receive frame sync output similar to pin 2

A transmit frame sync output similar to pin 1

A receive frame sync output similar to pin 2

4