DS2148 datasheet(22/75 Pages) DALLAS

22 / 75 page

DS2148/Q48

22 of 75

HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) Figure 4-3

5. HARDWARE MODE

In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for

initializing the DS2148. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The

RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic

0. The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11

while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at

pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The

transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). LOOP1 (pin 17)

and LOOP0 (pin 16) control the loopback functions. All other control bits default to the logic 0 setting.

1 EG L

2 ETS

3 NRZE

4 SCLKE

5 L2

6 L1

7 L0

8 DJA

9 JAMUX

10 JAS

11 HBE

BIS1 33

BIS0 32

BPCLK 31

MCLK 30

HRST* 29

RRING 28

RTIP 27

TEST 26

RCL 25

PBEO 24

RT1 23

DS2148

Hardware

Operation

tie high

DS2148 数据表(PDF) 22 Page - Dallas Semiconductor

DS2148 数据表(HTML) 22 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

数据表下载