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P9221-R 数据表(PDF) 10 Page - Integrated Device Technology

部件名 P9221-R
功能描述  Wireless Power Receiver for 15W Applications
PDF  35 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

P9221-R 数据表(HTML) 10 Page - Integrated Device Technology

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P9221-R Datasheet
© 2017 Integrated Device Technology, Inc.
10
April 4, 2017
Symbol
Description
Conditions
Min
Typical
Max
Units
VDD5V Voltage
VVDD5V
VDD5V Pin Output
Voltage[a]
IVDD5V = 10mA, CVDD5V = 1µF
4.5
5
5.5
V
Low Drop-Out (LDO) Regulator
IOUT_MAX
Maximum Output Current
1.25
A
VOUT_12V
12V Output Voltage
VOSET > 1.5V, VRECT=12.3V
12
V
VOUT_9V
9V Output Voltage
0.7V < VOSET < 1.2V, VRECT=9.3V
9
V
Analog to Digital Converter
N
Resolution
12
Bit
fSAMPLE
Sampling Rate
67.5
kSa/s
Channel
Number of Channels
8
VIN,FS
Full-Scale Input Voltage
2.1
V
EN
̅̅̅̅ pin
VIH
Input Threshold HIGH
1.4
V
VIL
Input Threshold LOW
0.25
V
IIL
Input Current LOW
VEN
¯¯ = 0V
-1
1
μA
IIH
Input Current HIGH
VEN
¯¯ = 5V
2.5
μA
VOSET, ILIM, TS, RPPO, RPPG
IIL
Input Current LOW
VVOSET, VILIM, VTS, VRPPO, VRPPG = 0V
-1
1
µA
IIH
Input Current HIGH
VVOSET, VILIM, VTS, VRPPO, VRPPG = 1.8V
-1
1
µA
ALIGNX, ALIGNY and INT
̅̅̅̅ pins
ILKG
Input Leakage Current
VALIGNX, VALIGNY, VINT = 0V and 5V
-1
1
µA
VOL
Output Logic LOW
IOL = 8mA
0.36
V
I2C Interface – SCL, SDA
VIL
Input Threshold LOW
0.7
V
VIH
Input Threshold HIGH
1.4
V
ILKG
Input Leakage Current
VSCL, VSDA = 0V and 5V
-1
1
µA
VOL
Output Logic LOW
IOL = 8mA
0.36
V
fSCL
Clock Frequency
400
kHz
tHD,STA
Hold Time (Repeated) for
START Condition
0.6
µs
tHD:DAT
Data Hold Time
0
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs



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