M95040-DF datasheet(19/46 Pages) STMICROELECTRONICS

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M950x0-W M950x0-R M950x0-DF

Instructions

6.3

Read Status Register (RDSR)

The Read Status Register instruction is used to read the Status Register.

As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current

state of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle

is terminated by driving Chip Select (S) high.

The Status Register is always readable, even if a Write or Write Status Register cycle is in

progress. During a Write Status Register cycle, the values of the non-volatile bits (BP0,

BP1) become available when a new RDSR instruction is executed, after completion of the

Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In

Progress (WIP)) are dynamically updated during the ongoing Write cycle.

It is possible to read the Status Register contents continuously, as described in Figure 9.

Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status register

are as follows:

6.3.1

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

6.3.2

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write or Write Status Register instruction is accepted.

Table 6. Status register format

BP1

BP0

WEL

WIP

Block Protect bits

Write Enable Latch bit

Write In Progress bit

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