M95040-DF datasheet(21/46 Pages) STMICROELECTRONICS

21 / 46 page

DocID6512 Rev 13

21/46

M950x0-W M950x0-R M950x0-DF

Instructions

6.4

Write Status Register (WRSR)

A Write Status Register (WRSR) instruction allows new values to be written to the Status

been executed.

The WRSR instruction is entered by driving Chip Select (S) low, sending the instruction

code followed by the data byte on Serial Data input (D), and driving the Chip Select (S)

signal high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that

latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).

Otherwise, the WRSR instruction is not executed.

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-

timed write cycle that takes tW to complete (as specified in Table 16: DC characteristics

(M950x0-W, device grade 6) to Table 19: AC characteristics (M950x0-R or M95040-DF,

device grade 6)). The instruction sequence is shown in Figure 10: Write Status Register

(WRSR) sequence.

While the Write Status Register cycle is in progress, the Status register may still be read to

check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write

cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also

reset at the end of the write cycle tW.

The WRSR instruction allows the user to change the values of the BP1, BP0 bits which

define the size of the area that is to be treated as read only, as defined in Table 3: Write-

protected block size. The contents of the BP1, BP0 bits are updated after the completion of

the WRSR instruction, including the tW write cycle.

The WRSR instruction has no effect on the b7, b6, b5, b4, b1 and b0 bits in the Status

Figure 10. Write Status Register (WRSR) sequence

The WRSR instruction is not accepted, and is not executed, under the following conditions:

•

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

•

if a write cycle is already in progress

•

if the device has not been deselected, by Chip Select (S) being driven high, after the

eighth bit, b0, of the data byte has been latched in

•

if Write Protect (W) is low during the WRSR command (instruction, address and data)

AI01445B

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

M95040-DF 数据表(PDF) 21 Page - STMicroelectronics

M95040-DF 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表下载