STHDLS101A datasheet(7/24 Pages) STMICROELECTRONICS

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STHDLS101A

Pin configuration

Doc ID 15756 Rev 1

7/24

3.1

Pin description

Table 2.

Pin description

number

Name

Type

Function

1GND

Power

Ground

VCC33

Power

3.3 V±10% DC supply

FUNCTION1

Vendor-specific

control or test

pins

Function pins are to enable vendor-specific features or

test modes. For normal operation, these pins are tied to

GND or VCC33

For consistent interoperability, GND is the preferred

default connection for these signals. Provides equalizer

6dB lift at high frequencies

FUNCTION2

Vendor-specific

control or test

pins

Function pins are to enable vendor-specific features or

test modes

For normal operation, these pins are tied to GND or

VCC33

For consistent interoperability, GND is the preferred

default connection for these signals. Provides 5 dB

equalizer gain at all frequencies

5GND

Power

Ground

REXT

Analog

Connection to external resistor. Resistor value

specified by device manufacturer.

Acceptable connections to this pin are:

– Resistor to GND

– Resistor to 3.3 V

– NC (direct connections to VCC or GND are through a

Ω resistor for layout compatibility

HPD_SOURCE

Output

Buffer from the 0 V to 5 V input signal. The output

buffer stage is configurable based on the FUNCTION3

pin settings as desribed in the table below:

FUNCTION3

HPD_SINK

HPD_SOURCE

0Low

Open-drain,

connected an

external pull up to

the desired

supply

(normally 1 V)

High (5 V)

Low (0 V)

High (5 V)

High (3 V)

SDA_SOURCE

I/O

3.3 V DDC data I/O. Pulled-up by external termination

to 3.3 V. Connected to SDA_SINK through voltage-

limiting integrated NMOS pass-gate

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