AS6C2016 datasheet(8/13 Pages) ALSC

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WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)

Dout

Din

Data Valid

tDW

tDH

(4)

High-Z

tWHZ

WE#

LB#,UB#

tCW

CE#

Address

tWR

tAS

tAW

tWC

tWP

tBW

Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance

state.

6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

128K X 16 BIT LOW POWER CMOS SRAM

FEBRUARY 2008

AS6C2016

FEBRUARY/2008, V 1.c

Alliance Memory Inc.

Page 8 of 13

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