M58LW64D datasheet(37/50 Pages) STMICROELECTRONICS

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M58LW064D

Table 28. Block Status Register

Note: 1. BA specifies the block address location, A22-A17.

2. In x8 mode, A0 must be set to VIL, otherwise 00h will be output.

3. Not Supported.

Table 29. Extended Query information

Address

Data

Selected Block Information

(BA+2)h(1,2)

bit0

Block Unprotected

Block Protected

bit1

Last erase operation ended successfully (3)

Last erase operation not ended successfully (3)

bit7-2

Reserved for future features

Address

Data (Hex)

Description

offset

x16

x8(2)

(P)h

0031h

62h

50h

"P"

Query ASCII string - Extended Table

(P+1)h

0032h

64h

52h

"R"

(P+2)h

0033h

66h

49h

"I"

(P+3)h

0034h

68h

31h

Major version number

(P+4)h

0035h

6Ah

31h

Minor version number

(P+5)h

0036h

6Ch

CEh

Optional Feature: (1=yes, 0=no)

bit0, Chip Erase Supported (0=no)

bit1, Suspend Erase Supported (1=yes)

bit2, Suspend Program Supported (1=yes)

bit3, Protect/Unprotect Supported (1=yes)

bit4, Queue Erase Supported (0=no)

bit5, Instant Individual Block locking (0=no)

bit6, Protection bits supported (1=yes)

bit7, Page Read supported (1=yes)

bit 8, Synchronous Read supported (0=no)

bits 9 to 31 reserved for future use

(P+6)h

0037h

6Eh

00h

(P+7)h

0038h

70h

00h

(P+8)h

0039h

72h

00h

(P+9)h

003Ah

74h

01h

Function allowed after Suspend:

Program allowed after Erase Suspend (1=yes)

Bit 7-1 reserved for future use

(P+A)h

003Bh

76h

01h

Block Status Register

bit0, Block Protect-Bit status active (1=yes)

bit1, Block Lock-Down Bit status (not available)

bits 2 to 15 reserved for future use

(P+B)h

003Ch

78h

00h

(P+C)h

003Dh

7Ah

33h

VDD OPTIMUM Program/Erase voltage conditions

(P+D)h

003Eh

7Ch

00h

VPP OPTIMUM Program/Erase voltage conditions

(P+E)h

003Fh

7Eh

01h

OTP protection: No. of protection register fields

(P+F)h

0040h

80h

Protection Register’s start address, least significant bits

(P+10)h

0041h

82h

00h

Protection Register’s start address, most significant bits

(P+11)h

0042h

84h

03h

n where 2n is number of factory reprogrammed bytes

(P+12)h

0043h

86h

03h

n where 2n is number of user programmable bytes

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