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STA311B 数据表(PDF) 13 Page - STMicroelectronics |
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STA311B 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 102 page  DocID024340 Rev 1 13/102 STA311B Device overview 102 Master volume override (MVO) This pin enables the user to bypass the volume control on all channels. When MVO is pulled high, the master volume register is set to 0x00, which corresponds to its full-scale setting. The master volume register setting offsets the individual channel volume settings, which default to 0 dB. Serial data in (SDI_12, SDI_34, SDI_56, SDI_78) Audio information enters the device here. Six format choices are available including I²S, left- justified or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. RESET Driving this pin low turns off the outputs and returns all settings to their defaults. I²C bus The SA, SDA and SCL pins operate per the Phillips I²C specification. See Section 7: I²C bus operation on page 23. 36 3.3-V capable TTL 2 mA output buffer OUT4A PWM channel 4 output A 37 3.3-V capable TTL 2 mA output buffer OUT3B PWM channel 3 output B 38 3.3-V capable TTL 2 mA output buffer OUT3A PWM channel 3 output A 41 3.3-V capable TTL 2 mA output buffer OUT2B PWM channel 2 output B 42 3.3-V capable TTL 2 mA output buffer OUT2A PWM channel 2 output A 43 3.3-V capable TTL 2 mA output buffer OUT1B PWM channel 1 output B 44 3.3-V capable TTL 2 mA output buffer OUT1A PWM channel 1 output A 45 3.3-V capable TTL 4 mA output buffer EAPD External amp power-down 48 3.3-V capable TTL 2 mA output buffer BICKO Output serial clock 49 3.3-V capable TTL 2 mA output buffer LRCKO Output left/right clock 50 3.3-V capable TTL 2 mA output buffer SDO_12 Output serial data channels 1&2 51 3.3-V capable TTL 2 mA output buffer SDO_34 Output serial data channels 3&4 54 3.3-V capable TTL 2 mA bidirectional buffer SDO_56 Output serial data channels 5&6 External power bridge fault input 55 3.3-V capable TTL 2mA output buffer SDO_78 Output serial data channels 7&8 External power bridge tristate signal (‘0’ = tristate) 56 5-V tolerant TTL Schmitt trigger input buffer PWDN Device power-down 3, 11,21,24, 31, 39, 46, 52 3.3-V digital supply voltage VDD 3.3-V supply 4, 12, 23, 32, 40, 47, 53 Digital ground GND Ground Table 2. Pin description (continued) Pin Type Name Description |
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