STA311B datasheet(21/102 Pages) STMICROELECTRONICS

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STA311B

Startup/shutdown pop noise removal in SE application

102

Startup/shutdown pop noise removal in SE

application

Click and pop can generally be defined as undesired audible transients generated by the

amplifier system not coming from the system input signal. Such transients can be generated

when the amplifier system changes its operating mode: system power-up/power-down,

mute/unmute. Every time the PWM starts or stops, if no soft charge method is applied, the

result is an audible pop noise.

The STA311B integrates a “pop-elimination” circuitry that removes undesired audible pop

noise at the PWM switching start and stop either in single-ended or single-ended virtual

ground configurations.

In particular the pop elimination circuit receives as inputs the PWMs generated by the

modulator (PWMs_in) and it generates both a delayed version of the PWMs (PWMs_out)

and a tristate signal that are sent to the Power stages to attenuate the audible pop at the

power up/down.

6.1

PWM start

At power-up as soon as the external amplifier power-down (EAPD) is set to one, if at least

one channel at the output of the modulator is in binary mode, the pop elimination circuit

selects the related PWM input which exhibits the lower PWM timing delay (set using the I²C

registers 0x33, 0x34,0x35, 0x36), and it uses it as a PWM reference to synchronize the

remaining PWMs_in whose channels are set in binary mode (synchronization phase).

Moreover, during the synchronization phase the modulator is internally muted by setting the

audio input signal to

zero. At the end of this phase, all the PWMs_in are synchronous with the PWM reference

and they have a duty cycle of 50%.

At each rising edge of the PWM reference, twoTristate_ramp pulses with increasing duty

cycle are generated. As depicted in Figure 10, where for the sake of simplicity, only two

PWMs_in (PWM1_in and PWM2_in) are shown, each pulse is centered with respect to both

the rising and falling edges of the PWM reference, and their duty cycle initially set to 21.87%

increases gradually and becomes equal to 100% at the end of theTristate_ramp.

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